1. Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to the structure of a semiconductor device having both dynamic random access memories (DRAM) and logic circuits on the same substrate.
2. Description of the Related Art
FIGS. 29(A) to 38 are diagrams illustrating a conventional method of manufacturing a semiconductor device with DRAM and logic circuits.
In each figure, the right side shows a CMOS transistor area in a logic area, and the left side shows a DRAM memory area.
First, as shown in FIG. 29(A), element isolation regions 102 are formed on a silicon substrate 101 by well-known element isolation techniques such as shallow trench isolation (STI) techniques to separate active regions.
If necessary, n-wells are formed in a p-channel transistor area and p-wells are formed in an n-channel transistor area and a memory cell area. A channel stop layer for preventing leak current between element forming regions and a channel dope layer for controlling Vth are also formed. Three masks (resist patterns) in total are required to form a p-well and an n-well in the logic area and a p-well in the memory cell area by using different ion implantation. If a triple well is to be formed, four masks in total are required.
Next, as shown in FIG. 29(B), a gate oxide film Gox is formed on the active region through thermal oxidation, and an amorphous silicon layer 103 is formed on the gate oxide film Gox. A resist pattern 104 exposing the n-channel transistor area and memory cell area is formed on the amorphous silicon layer 103. Arsenic or phosphorous ions are implanted to change the n-channel transistor area and memory cell area of the amorphous silicon layer 103 to an n-type amorphous silicon layer 103a. In the following drawings, the gate oxide film Gox is omitted.
As shown in FIG. 30(A), after the resist pattern 104 is removed, a resist pattern 105 exposing the p-channel transistor area is newly deposited. Boron or boron fluoride ions are implanted to change the amorphous silicon layer 103 on the p-channel region to a p-type amorphous silicon layer 103b. 
By implanting n-type impurities into the silicon layer to be used as the gate in the n-channel transistor area and p-type impurities into the silicon layer to be used as the gate in the p-channel transistor area, as described above, resistance against the short channel effects can be made high because surface channel type transistors can be formed by utilizing a work function difference. This structure requires two masks (resist patterns).
As shown in FIG. 30(B), after the resist pattern 105 is removed, a tungsten silicide (WSi) layer 106 and a silicon nitride film 107 are sequentially deposited by chemical vapor deposition (CVD), and patterned into a gate electrode shape by well-known photolithography techniques. The gate electrode in the memory cell area also functions as a word line.
As shown in FIG. 31(A), a resist pattern 108 exposing the p-channel transistor area is formed. Boron ions are implanted into the substrate to form a lightly doped drain (LDD) regions (p− type impurity diffusion layer) 109 of a p-channel transistor.
As shown in FIG. 31(B), after the resist pattern 108 is removed, a resist pattern 110 is formed to expose the n-channel transistor area in the logic area. Phosphorous ions are implanted into the substrate to form a low concentration regions (LDD regions, n-type impurity diffusion regions) 111 of an n-channel transistor.
As shown in FIG. 32(A), after the resist pattern 110 is removed, a resist pattern 112 is formed to expose the memory cell area. Phosphorous ions are implanted into the substrate to form an n-type impurity diffusion regions (source/drain regions) 113 of a transistor in the memory cell area.
Next, as shown in FIG. 32(B), after the resist pattern 112 is removed and a silicon nitride film 114 is formed, the memory cell area is covered with a resist pattern 115 to anisotropically and selectively etch the nitride film in the CMOS area. The nitride film on the flat surface is removed to form side wall spacers 114a on the side walls of the gate electrodes of n- and p-channel transistors in the CMOS area.
In this case, the source/drain regions in the memory cell area are being covered with the silicon nitride film.
Next, similar to the processes shown in FIGS. 31(A) and 31(B), by using different resist patterns, boron ions are implanted into the p-channel transistor area to a high concentration and arsenic ions are implanted into the n-channel transistor area to a high concentration to form source/drain regions (p+-type impurity diffusion regions 116 and n+-type impurity diffusion regions 117), as shown in FIG. 33. Thereafter, the resist pattern used as the mask is removed.
Next, a cobalt (Co) film is formed on the surface of the semiconductor substrate by sputtering, and heat treatment is performed to react Co with the exposed silicon surface. Then, unreacted cobalt film is removed. With these processes, a cobalt silicide layer 118 is formed on the source/drain regions 116 and 117 in the CMOS area. A process of forming the suicide layer through reaction between exposed silicon and cobalt and removing the unreacted metal layer to from the silicide layer only on the silicon area is called a salicide (self-aligned silicide) process.
As shown in FIG. 34, after a BPSG layer 119 is formed by CVD, the surface of this layer is planarized by a chemical mechanical polishing (CMP) method or the like. Next, contact holes 120 are formed through the BPSG layer 119 in the areas corresponding to the source/drain regions 113 by well-known photolithography techniques. In this case, BPSG is etched under the conditions that the nitride film is hard to be etched, and the exposed nitride film is anisotropically etched to expose the surfaces of the source/drain regions 113 in the memory cell area.
The contact holes 120 can be formed in self-alignment with the side wall spacers 114b because these spacers of nitride are formed on the side walls of the gate electrode to be used also as the word line. A process of forming a contact hole by utilizing an insulating film on the side walls of a wiring layer is generally called a SAC (self-aligned contact) method.
As shown in FIG. 35, a silicon film is formed on the BPSG layer 119, filling the contact holes 120. Thereafter, the surface of the semiconductor substrate is planarized to remove the silicon film in the area other than the contact holes and leave the silicon layer only in the contact holes 120, so that silicon plugs 121 can be formed. Next, another BPSG layer 122 is formed and by using a resist pattern, a contact hole is formed through the BPSG layer 122 in the area corresponding to the silicon plug 121 to be connected to a bit line. A bit line 123 of tungsten or the like is formed and connected to the silicon plug 121 via the contact hole.
As shown in FIG. 36, a BPSG layer 124 is formed and the surface thereof is planarized. Contact holes for a storage electrode are formed through the BPSG layer 124 in areas corresponding to the silicon plugs 121 on both sides of the plug 121 connected to the bit line. Then, a storage electrode 125, a capacitor dielectric film 130 and an opposing electrode 126 are formed.
As shown in FIG. 37, after a BPSG layer 127 is formed over the capacitor, contact holes for the source/drain regions 116 and 117 in the CMOS area are formed through the BPSG layer 127. Al wiring layers 128 are formed on the BPSG layer 127, the Al wiring layers 128 being connected via the contact holes to the source/drain regions 116 and 117 in the CMOS area.
Thereafter, a passivation film is formed, bonding openings are formed and other necessary processes are executed by well-known methods to complete a CMOS logic-memory device.
The above-described conventional processes are, however, associated with the following problems.
First, the SAC process becomes necessary in the cell area in order to reduce a memory cell area, and in order to form high performance transistors, the CMOS structure in the logic area is required to be of the surface channel type for both n- and p-channel transistors and in addition the resistance of the electrode is required to be made low.
The number of processes therefore increases. Ten photolithography processes are used from the doping process of the gate electrode shown in FIG. 29(B) to the contact hole forming process for the source/drain regions in the memory cell area shown in FIG. 34. If photolithography processes for forming the wells are added, thirteen photolithography processes are used.
Second, it is technically difficult to form contact holes for the gate electrodes in the memory cell area and logic area at the same time when contact holes for the source/drain regions are formed in the logic area by using the highest level Al layer.
This problem is illustrated in FIG. 38. The left side portion shows a contact region between the gate electrode and Al wiring layer in the memory cell area, the center portion shows a contact region between the gate electrode in the logic area and the Al wiring layer, and the right portion shows a contact region between the source/drain regions in the n-channel transistor area in the logic area and the Al wiring layer. The Al wiring layer in the memory cell area contacts, for example, the low level word line constituting a strap word line for the Al wiring layer.
As seen from FIG. 38, in the source/drain contact portion in the logic area of the right side portion, contact holes are formed by etching the BPSG films 127, 124, 122 and 119, whereas in the gate electrode contact portion of the center portion, contact holes are formed by etching the BPSG films 127, 124, 122 and 119 and in addition the silicon nitride film 107. In addition to these films, the silicon nitride film 114 is required to be etched in the gate electrode contact portion in the left memory cell area.
If these contact holes are to be formed at the same time, BPSG over the source/drain regions in the logic area is completely etched while the nitride film 114 or 107 is etched. The contact holes are therefore formed through the silicide layer 118 and source/drain regions 117 and enter the substrate 101. From this reason, these contact holes cannot be formed at the same time. It is necessary to further increase the number of photolithography processes.
Third, since the silicon nitride film is in direct contact with the side walls of the gate electrode, particularly with the gate electrode in the logic area, transistor characteristics are likely to be deteriorated by hot carriers. Further, because of hydrogen (H) in the nitride film, boron ions implanted into the gate electrode in the p-channel transistor area enter the gate insulating film so that the threshold value (Vth) of the transistor may be varied. Therefore, the transistor characteristics are varied and the manufacture yield is lowered.